1. Field of the Invention
The present invention relates to a method for isolating, and more particularly to a method for fabricating an isolation trench applied in BiCMOS processes.
2. Description of the Prior Art
Referring to FIG. 1a to FIG. 1e to FIG. 1a conventional method for fabricating an isolation trench applied in BiCMOS processes is schematically depicted in cross-sectional views.
Referring to FIG. 1a, a semiconductor substrate 10 such as a P-type silicon substrate 10 is provided. Subsequently, a bipolar junction transistor region BJT, and MOS transistor regions T1 and T2 are defined by the conventional steps of forming a pre-doping oxide layer, alignment, and etching, wherein the MOS transistor region T2 is formed between the bipolar junction transistor region BJT and the MOS transistor region T1. Thereafter, N.sup.+ -type ions and P.sup.+ -type ions are doped into the bipolar junction transistor region BJT and the MOS transistor region T1 to form N.sup.+ -type buried layers 12 and 16, and to form a P.sup.+ -type buried layer 14 in the MOS transistor region T2, respectively. An epitaxy layer 20 such as an N-type epitaxy layer is then formed on the silicon substrate 10.
Referring to FIG. 1b, N wells (N-W) 12a and 16a are formed in the epitaxy layer 20 above the N+-type buried layers 12 and 16. For example, a pre-doping oxide layer 30 is formed on the epitaxy layer 20 by thermal oxidation. A photoresist layer (not shown) is then coated on the pre-doping oxide layer 30, and a patterned photoresist layer PR1 is formed by exposure and development steps, so that the pre-doping oxide layer 30 above the N.sup.+ -type buried layers 12 and 16 is exposed. Subsequently, N wells (N-W) 12a and 16a are formed in the epitaxy layer 20 above the N.sup.+ -type buried layers 12 and 16 by doping N-type ions into the epitaxy layer 20
Referring to FIG. 1c, the photoresist layer PR1 is removed, and a photoresist layer PR2 is formed and patterned on the pre-doping oxide layer 30 so that the pre-doping oxide layer 30 above a region that is to be a collector region in the N well 12a is exposed. Subsequently, a collector region C is formed by doping N.sup.+ -type ions into the N well 12a.
Referring to FIG. 1d, the patterned photoresist layer PR2 and the pre-doping oxide layer 30 are removed, and a pad oxide layer 40 is then formed on the epitaxy layer 20. Subsequently, a silicon nitride layer 50 is formed and defined by photolithography and etching processes to form openings 60 exposing the pad oxide layer 40.
Referring to FIG. 1e, a photoresist layer PR3 is coated and patterned to expose the pad oxide layer 40 and the patterned silicon nitride layer 50 above a region that is to be a P well. Thereafter, a P well 14a is formed by doping P.sup.+ -type ions into the epitaxy layer 20 above the P.sup.+ -type buried layer 14.
Referring to FIG. 1f, the patterned photoresist layer PR3 is removed, and field oxide layers 601 are formed in the openings 60 by local oxidation (LOCOS). Subsequently, the patterned silicon nitride layer 50 is removed.
The method as described above mainly utilizes the field oxide layer to isolate the N well, the collector region, and the P well, thereby decreasing the junction capacitance. However, the field oxide layer causes the Bird's Beak effect so that the integration of the semiconductor can't be increased. Furthermore, the isolating effect is poor.